1. Field of the Invention
The present invention relates to a computer-aided design (CAD) method and a CAD tool executing the CAD method. It is particularly related to the CAD method and the CAD tool of a semiconductor integrated circuit having a multi-level interconnection, with a plurality of logic cells and power supply wirings that supply the logic cells with electric power, and a semiconductor integrated circuit manufactured with mask patterns designed by the CAD method and the CAD tool.
2. Description of the Related Art
In earlier technology, along each side of a silicon chip, or a single crystal substrate (semiconductor chip) cut into a rectangular geometry in a plan view, multiple of chip-site bonding pads (external input/output terminals) are arranged so as to implement a semiconductor integrated circuit, which adopts a mesh architecture for a power supply system. Inside the array of chip-site bonding pads, input/output buffer cells (I/O cells) are arranged corresponding to the array of chip-site bonding pads at the periphery of the semiconductor chip. The central portion of the semiconductor chip surrounded by the input/output buffer cells is defined as “a logic element arrangement region” for placing macrocells (functional blocks) having logic or memory functions and/or logic cells (logic elements).
Horizontal power supply wirings and vertical power supply wirings are arranged so as to form a mesh topology in the logic element arrangement region, supplying power to the macrocells and/or the logic cells. Horizontal power supply wirings in a subject wiring level crisscross with vertical power supply wirings disposed in an upper or lower wiring level of the subject wiring level so as to implement a multi-level interconnection architecture.
For example, a structure of a five level interconnection can be implemented by a first high-potential power supply wiring extending along the X direction in a first wiring level, or in the lowest level, a second high-potential power supply wiring extending along the Y direction in a second wiring level, a third high-potential power supply wiring extending along the X direction in a third wiring level, a fourth high-potential power supply wiring extending along the Y direction in a fourth wiring level and a fifth high-potential power supply wiring extending along the X direction in a fifth wiring level, or in the upper most level. In the five level interconnection, power is supplied from the fifth high-potential power supply wiring to the fourth high-potential power supply wiring, the third high-potential power supply wiring, the second high-potential power supply wiring in order and finally to the first high-potential power supply wiring. Then power is supplied from the fifth high-potential power supply wiring to the logic cell (logic element).
The interlevel between the fifth high-potential power supply wiring and the fourth high-potential power supply wiring is electrically connected through a via-hole (or through-hole) penetrating an interlevel insulator formed between the fifth and fourth high-potential power supply wirings. Similarly, each of the interlevels is electrically connected through a via-hole between the fourth and third high-potential power supply wirings, between the third and second high-potential power supply wirings, between the second and first high-potential power supply wirings.
In general, in earlier CAD technology for designing semiconductor integrated circuits, implemented by such mesh architecture, power supply wirings are allocated uniformly in the whole area of the logic element arrangement region. Therefore, as current dissipation increases, due to the advance of performance and the increase of the number of logic cells in a semiconductor integrated circuit, the number of power supply wirings tends to increase. Then, as the performance of semiconductor integrated circuits improves and the degree of on-chip integration increases, the real estate, or the area of the arrangement region (routing space) of signal wirings routing the macrocells and the logic cells (logic elements), etc. decreases, and wiring efficiency of the signal wirings decreases.
In earlier physical designs of semiconductor integrated circuits based upon mesh architecture, an analysis process of electro-migration immunity and voltage drop of power supply wirings is performed, after the placement process of the power supply wirings, the macrocells, the logic cells (logic elements) etc. And, as a result of the analysis process, a supplemental power supply wiring is added if sufficient electro-migration immunity is not obtained or voltage drop exceeds a tolerable value. Also after macrocells, logic cells (logic elements), power supply wirings etc. were placed and completing a layout design, there arose a case where improvements in operation timing and circuit change etc. are required, so that engineering change order (ECO) must be executed. Owing to the execution of the ECO, by which the addition and/or resizing of a logic cell (logic element) may be conducted, current dissipation increases in a localized part of the semiconductor integrated circuit, and a further supplemental power supply wiring must be added.
However, addition of such supplemental power supply wiring is difficult, because routing process of clock signal wirings and other signal wirings is already finished in a semiconductor integrated circuit of a mesh architecture. For example, when a supplemental power supply wiring must be added, in order to prevent electrical short circuit failure between the supplemental power supply wiring and clock signal wirings or between the supplemental power supply wiring and other signal wirings, the clock signal wirings and other signal wirings may be required to be moved. And when the clock signal wirings and other signal wirings are moved, change of operation timing is generated. That is to say, a technical problem occurs such that, to some extent, redesign of the layout is inevitable in advanced semiconductor integrated circuits.
In view of the technical problem, a semiconductor integrated circuit implemented by a stacked-via architecture is developed. In the semiconductor integrated circuit implemented by the stacked-via architecture, a plurality of chip-site bonding pads (external input/output terminals) are arranged along each side of a semiconductor chip, similar to the layout of the semiconductor integrated circuit implemented by the mesh architecture. Then, within the array of chip-site bonding pads (external input/output terminals), input/output buffer cells are arranged. In the stacked-via architecture, the central portion surrounded by input/output buffer cells is the logic element arrangement region, in which a macrocell, having a logic function and/or a memory function, and logic cells (logic elements) are placed.
For example, consider the multi-level interconnection of five wiring levels, in which power is supplied from an upper high-potential power supply wiring of a fifth wiring level to a lower high-potential power supply wiring of a first wiring level through a stacked-via so that the power can be supplied to logic elements arranged in the logic element arrangement region of the semiconductor integrated circuit. To describe the stacked-via architecture, for example, suppose that the lower high-potential power supply wiring in the first wiring level extends along the X direction and that the upper high-potential power supply wiring in the fifth wiring level extends along the X direction, identical direction of the lower high-potential power supply wiring. Then, a stacked-via penetrates the triple interlevel insulators between the lower high-potential power supply wiring and the upper high-potential power supply wiring so that the lower high-potential power supply wiring and the upper high-potential power supply wiring can be electrically connected by the stacked-via. Therefore, the stacked-via may encompass a lowest via-plug of the second wiring level, a middle via-plug of the third wiring level disposed on the lowest via-plug and an upper via-plug of the fourth wiring level disposed on the middle via-plug. Namely, the stacked-via is implemented by vertically accumulating the lowest via-plug, the middle via-plug and the upper via-plug at identical position in a plan view.
However, physical design of a semiconductor integrated circuit implemented by the stacked-via architecture has following new problems:
(i) After vias were uniformly arranged in the whole area of the logic element arrangement region, a macrocell and logic cells (logic elements), etc. are placed actually, and then logic functions and memory functions are constructed by the macrocell and logic cells (logic elements), etc. But, because there is a considerable distance between a central portion of the logic element arrangement region and an I/O cell position for power supply, a resistance component of power supply wirings becomes so large in the central portion of the logic element arrangement region that the current is highly dissipated in the power supply wirings. Therefore, in the central portion, the power supply quantity is insufficient, and the drop of supply voltage is easily generated. In the meantime, in a crowded area where logic elements are packed in the logic element arrangement region, since the current dissipation by the logic elements is large, the power supply quantity from the stacked-vias is insufficient, and the drop of supply voltage is easily generated.
(ii) Consequently, in the above-stated crowded area of the logic cells (logic elements), because the number of allocated stacked-vias becomes relatively insufficient, excess current larger than the tolerable current for a single stacked-via easily flows in each of stacked-vias. Therefore, electro-migration is easily generated in the stacked-vias.
(iii) Since the stacked-vias are uniformly allocated in the whole area of the logic element arrangement region, in an area where logic cells (logic elements) are sparsely allocated with small allocation number of the logic cells (logic elements), the stacked-vias are allocated excessively larger than the required allocation number of the stacked-vias. Therefore, routing process of the signal wirings is restricted by the excessive stacked-vias and wiring efficiency decreases, disturbing the performance improvement, and the enhancement of high integration of the semiconductor integrated circuit becomes difficult.